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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-03 22:21:26 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-05 00:20:28 -0600 |
| commit | 3d63b06faee13536710fc7db08979797182684fb (patch) | |
| tree | bd64954f22fe389f4a9b7dada265e331003848f2 /riscv/execute.cc | |
| parent | 0eec0c911933ccc722d4b4479a6c4b8ac68f2f52 (diff) | |
| download | riscv-isa-sim-3d63b06faee13536710fc7db08979797182684fb.zip riscv-isa-sim-3d63b06faee13536710fc7db08979797182684fb.tar.gz riscv-isa-sim-3d63b06faee13536710fc7db08979797182684fb.tar.bz2 | |
Only update histogram when histogramming
This is worth a 1.4x speedup on the slow path (when not histogramming).
Diffstat (limited to 'riscv/execute.cc')
| -rw-r--r-- | riscv/execute.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index cd6ae1a..844f2b8 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -152,7 +152,8 @@ static void commit_log_print_insn(processor_t *p, reg_t pc, insn_t insn) inline void processor_t::update_histogram(reg_t UNUSED pc) { - pc_histogram[pc]++; + if (histogram_enabled) + pc_histogram[pc]++; } // These two functions are expected to be inlined by the compiler separately in |