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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-06-02 20:14:39 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-06-04 02:06:02 -0700 |
commit | 57e88c7e9ccc33757020122d2d7b20fe0b7c898c (patch) | |
tree | 6dcab142af4261c9fd73e11337f28c475ed1a4cd /riscv/encoding.h | |
parent | 3dc70c4bc7d5951f652e9fef50493d5346d5c799 (diff) | |
download | riscv-isa-sim-57e88c7e9ccc33757020122d2d7b20fe0b7c898c.zip riscv-isa-sim-57e88c7e9ccc33757020122d2d7b20fe0b7c898c.tar.gz riscv-isa-sim-57e88c7e9ccc33757020122d2d7b20fe0b7c898c.tar.bz2 |
encoding: udpate and move platform-related define out
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/encoding.h')
-rw-r--r-- | riscv/encoding.h | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 55088d6..7c02e14 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in - * https://github.com/riscv/riscv-opcodes (e8f0392) + * https://github.com/riscv/riscv-opcodes (7d1a0e3) */ /* See LICENSE for license details. */ @@ -211,12 +211,6 @@ #define IRQ_COP 12 #define IRQ_HOST 13 -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - /* page table entry (PTE) fields */ #define PTE_V 0x001 /* Valid */ #define PTE_R 0x002 /* Read */ |