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| author | Andrew Waterman <andrew@sifive.com> | 2022-02-04 16:54:19 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-02-04 16:54:19 -0800 |
| commit | e03fa93c988ec92b6f1427b5cc10c40b41351e70 (patch) | |
| tree | a0bafa986af9e69f8b17465e72055cd7a8807b07 /riscv/disasm.h | |
| parent | 1422fef66786fa1f0fa8d507251a0b334ef91362 (diff) | |
| download | riscv-isa-sim-e03fa93c988ec92b6f1427b5cc10c40b41351e70.zip riscv-isa-sim-e03fa93c988ec92b6f1427b5cc10c40b41351e70.tar.gz riscv-isa-sim-e03fa93c988ec92b6f1427b5cc10c40b41351e70.tar.bz2 | |
Improve fallback disassembly for disabled ISA strings
It's helpful to attempt to disassemble instructions for disabled
extensions, so attempt to do so. Since some extensions conflict
in the opcode space, continue to give higher priorty to explicitly
enabled extensions.
Diffstat (limited to 'riscv/disasm.h')
| -rw-r--r-- | riscv/disasm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/disasm.h b/riscv/disasm.h index a092f40..9957ce0 100644 --- a/riscv/disasm.h +++ b/riscv/disasm.h @@ -93,6 +93,8 @@ class disassembler_t static const int HASH_SIZE = 255; std::vector<const disasm_insn_t*> chain[HASH_SIZE+1]; + void add_instructions(isa_parser_t* isa); + const disasm_insn_t* probe_once(insn_t insn, size_t idx) const; static const unsigned int MASK1 = 0x7f; |