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| author | Andrew Waterman <andrew@sifive.com> | 2020-09-15 10:43:30 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-09-15 10:43:30 -0700 |
| commit | a3376ff9af100f6f58ebdb18864eda6ac68b51af (patch) | |
| tree | 8e6478169bfa669371986f33a45976a3d594fa56 /riscv/decode.h | |
| parent | 8957a8efec78ba7ad59a8719366a14a0674a1ee4 (diff) | |
| download | riscv-isa-sim-a3376ff9af100f6f58ebdb18864eda6ac68b51af.zip riscv-isa-sim-a3376ff9af100f6f58ebdb18864eda6ac68b51af.tar.gz riscv-isa-sim-a3376ff9af100f6f58ebdb18864eda6ac68b51af.tar.bz2 | |
Populate tval registers on illegal-/virtual-instruction traps
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 430fd08..83ba661 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -224,15 +224,15 @@ private: #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ if(rm == 7) rm = STATE.frm; \ - if(rm > 4) throw trap_illegal_instruction(0); \ + if(rm > 4) throw trap_illegal_instruction(insn.bits()); \ rm; }) #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) -#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0) +#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(insn.bits()) #define require_privilege(p) require(STATE.prv >= (p)) -#define require_novirt() if (unlikely(STATE.v == true)) throw trap_virtual_instruction(0) +#define require_novirt() if (unlikely(STATE.v)) throw trap_virtual_instruction(insn.bits()) #define require_rv64 require(xlen == 64) #define require_rv32 require(xlen == 32) #define require_extension(s) require(p->supports_extension(s)) @@ -360,14 +360,14 @@ inline freg_t f128_negate(freg_t a) bool mode_unsupported = (csr_priv == PRV_S && !P.supports_extension('S')) || \ (csr_priv == PRV_HS && !P.supports_extension('H')); \ if (mode_unsupported) \ - throw trap_illegal_instruction(0); \ + throw trap_illegal_instruction(insn.bits()); \ unsigned state_prv = (STATE.prv == PRV_S && !STATE.v) ? PRV_HS: STATE.prv; \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ if (((write) && csr_read_only) || state_prv < csr_priv) { \ if (csr_priv == PRV_HS) \ - throw trap_virtual_instruction(0); \ + throw trap_virtual_instruction(insn.bits()); \ else \ - throw trap_illegal_instruction(0); \ + throw trap_illegal_instruction(insn.bits()); \ } \ (which); }) |