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authorAndrew Waterman <andrew@sifive.com>2022-10-19 21:40:42 -0700
committerAndrew Waterman <andrew@sifive.com>2022-10-19 21:40:42 -0700
commitb1f2ae41a1e64f416fb5f5aa092352439ecefa83 (patch)
treea5918c9e5ff22fb72c568f9751602ebbd8974d0f /riscv/debug_module.cc
parentd41af9f81cb393ed6fad8b9cb756a5b459e7c9ab (diff)
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Template-ize stores
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r--riscv/debug_module.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 341cd04..2f48dd2 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -340,13 +340,13 @@ void debug_module_t::sb_write()
reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
if (sbcs.sbaccess == 0 && config.max_sba_data_width >= 8) {
- sim->debug_mmu->store_uint8(address, sbdata[0]);
+ sim->debug_mmu->store<uint8_t>(address, sbdata[0]);
} else if (sbcs.sbaccess == 1 && config.max_sba_data_width >= 16) {
- sim->debug_mmu->store_uint16(address, sbdata[0]);
+ sim->debug_mmu->store<uint16_t>(address, sbdata[0]);
} else if (sbcs.sbaccess == 2 && config.max_sba_data_width >= 32) {
- sim->debug_mmu->store_uint32(address, sbdata[0]);
+ sim->debug_mmu->store<uint32_t>(address, sbdata[0]);
} else if (sbcs.sbaccess == 3 && config.max_sba_data_width >= 64) {
- sim->debug_mmu->store_uint64(address,
+ sim->debug_mmu->store<uint64_t>(address,
(((uint64_t) sbdata[1]) << 32) | sbdata[0]);
} else {
sbcs.error = 3;