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| author | Tim Newsome <tim@sifive.com> | 2023-09-28 09:08:25 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-09-28 09:08:25 -0700 |
| commit | 77e9aaef19f528d8ced2301fe39eb941a9fdc3e2 (patch) | |
| tree | b80012034d67c4335f83bcfa47a9c5a49a7e7ec0 /riscv/debug_module.cc | |
| parent | 7613da4d26dbaaf9063540187a4a880cb3c0b3e9 (diff) | |
| download | riscv-isa-sim-77e9aaef19f528d8ced2301fe39eb941a9fdc3e2.zip riscv-isa-sim-77e9aaef19f528d8ced2301fe39eb941a9fdc3e2.tar.gz riscv-isa-sim-77e9aaef19f528d8ced2301fe39eb941a9fdc3e2.tar.bz2 | |
debug: Abstract commands fail on unavailable harts.
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 026f4b3..e9aef1a 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -579,6 +579,10 @@ bool debug_module_t::perform_abstract_command() abstractcs.cmderr = CMDERR_BUSY; return true; } + if (!hart_available(dmcontrol.hartsel)) { + abstractcs.cmderr = CMDERR_HALTRESUME; + return true; + } if ((command >> 24) == 0) { // register access |