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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-22 21:25:27 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-01-22 21:26:47 +0800 |
| commit | 78ee489d5a6597075558f6ef9507b9d01a3bb32d (patch) | |
| tree | 81d0d659fcc3a4b00fb8604a54d6cd4fdb74b667 /riscv/debug_defines.h | |
| parent | 3482790b260ed34db9a19f3bd18a3f93b6573342 (diff) | |
| download | riscv-isa-sim-78ee489d5a6597075558f6ef9507b9d01a3bb32d.zip riscv-isa-sim-78ee489d5a6597075558f6ef9507b9d01a3bb32d.tar.gz riscv-isa-sim-78ee489d5a6597075558f6ef9507b9d01a3bb32d.tar.bz2 | |
fix redefinition of CSR_MCONTEXT and CSR_SCONTEXT
Diffstat (limited to 'riscv/debug_defines.h')
| -rw-r--r-- | riscv/debug_defines.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/debug_defines.h b/riscv/debug_defines.h index e6c2c5d..1f7e0b7 100644 --- a/riscv/debug_defines.h +++ b/riscv/debug_defines.h @@ -403,7 +403,6 @@ #define CSR_TCONTROL_MTE_OFFSET 3 #define CSR_TCONTROL_MTE_LENGTH 1 #define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET) -#define CSR_MCONTEXT 0x7a8 /* * Machine mode software can write a context number to this register, * which can be used to set triggers that only fire in that specific @@ -416,7 +415,6 @@ #define CSR_MCONTEXT_MCONTEXT_OFFSET 0 #define CSR_MCONTEXT_MCONTEXT_LENGTH XLEN #define CSR_MCONTEXT_MCONTEXT (((1L<<XLEN)-1) << CSR_MCONTEXT_MCONTEXT_OFFSET) -#define CSR_SCONTEXT 0x7aa /* * Supervisor mode software can write a context number to this * register, which can be used to set triggers that only fire in that |