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| author | Andrew Waterman <andrew@sifive.com> | 2024-04-29 14:54:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-29 14:54:36 -0700 |
| commit | d39cbb3ad27b2de882260c0a22f11a59efebb151 (patch) | |
| tree | 5ca3e32d2bbe8a8da9b978c43aab6880fedb140a /riscv/cfg.h | |
| parent | bfe1d76608448ed668315b67723de538eac7ecb3 (diff) | |
| parent | e77c918ff3a5aa63ad459eff6b10a6ee0647451f (diff) | |
| download | riscv-isa-sim-d39cbb3ad27b2de882260c0a22f11a59efebb151.zip riscv-isa-sim-d39cbb3ad27b2de882260c0a22f11a59efebb151.tar.gz riscv-isa-sim-d39cbb3ad27b2de882260c0a22f11a59efebb151.tar.bz2 | |
Merge pull request #1648 from YenHaoChen/pr-hstateen
Smstateen: Ignore writes to read-only hstateen*[n] bits when mstateen*[n]=0
Diffstat (limited to 'riscv/cfg.h')
0 files changed, 0 insertions, 0 deletions