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| author | Megan Wachs <megan@sifive.com> | 2020-02-11 12:35:51 -0800 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2020-02-11 12:35:59 -0800 |
| commit | b8eb9cd50da527d8ac280f818baa5473ab21da91 (patch) | |
| tree | 6d1a7c0bfd88f2d96b4e8efdb9a7d762837eeb24 /fesvr/option_parser.cc | |
| parent | ab141b814daf778597b106c155fd8c011be90f10 (diff) | |
| download | riscv-isa-sim-b8eb9cd50da527d8ac280f818baa5473ab21da91.zip riscv-isa-sim-b8eb9cd50da527d8ac280f818baa5473ab21da91.tar.gz riscv-isa-sim-b8eb9cd50da527d8ac280f818baa5473ab21da91.tar.bz2 | |
FESVR: ensure dmactive is 1 before reading debug module registers
Diffstat (limited to 'fesvr/option_parser.cc')
0 files changed, 0 insertions, 0 deletions