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author | Yueh-Ting (eop) Chen <eop.chen@sifive.com> | 2021-12-28 12:19:25 +0800 |
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committer | GitHub <noreply@github.com> | 2021-12-27 20:19:25 -0800 |
commit | d750d6a92bac6423eb4d9a390cab5a6dfbff9f37 (patch) | |
tree | f028f2e6f44999146ff4e9cb80bc69d75a42c208 /disasm | |
parent | cfcf083a8f7cba552cfdd1b9c2618d2302c0889d (diff) | |
download | riscv-isa-sim-d750d6a92bac6423eb4d9a390cab5a6dfbff9f37.zip riscv-isa-sim-d750d6a92bac6423eb4d9a390cab5a6dfbff9f37.tar.gz riscv-isa-sim-d750d6a92bac6423eb4d9a390cab5a6dfbff9f37.tar.bz2 |
Update instruction vmandnot.mm, vmornot.mm -> vmandn.mm, vmorn.mm (#896)
Refer to rvv-spec v1.0-rc2
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 9e26f0f..53f71fa 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1322,11 +1322,11 @@ disassembler_t::disassembler_t(int xlen) DISASM_INSN("vcompress.vm", vcompress_vm, 0, {&vd, &vs2, &vs1}); - DISASM_OPIV_M___INSN(vmandnot, 1); + DISASM_OPIV_M___INSN(vmandn, 1); DISASM_OPIV_M___INSN(vmand, 1); DISASM_OPIV_M___INSN(vmor, 1); DISASM_OPIV_M___INSN(vmxor, 1); - DISASM_OPIV_M___INSN(vmornot, 1); + DISASM_OPIV_M___INSN(vmorn, 1); DISASM_OPIV_M___INSN(vmnand, 1); DISASM_OPIV_M___INSN(vmnor, 1); DISASM_OPIV_M___INSN(vmxnor, 1); |