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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-06-18 22:50:46 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-06-19 11:39:49 -0700 |
| commit | d6d919ee5b061add58b159b6551235241744c91f (patch) | |
| tree | e8e83e545b78e5fc941c88bede5ff612f98814f5 /disasm | |
| parent | 6c9168c8df30d8345bf6f9de6e8118c3c3b77cee (diff) | |
| download | riscv-isa-sim-d6d919ee5b061add58b159b6551235241744c91f.zip riscv-isa-sim-d6d919ee5b061add58b159b6551235241744c91f.tar.gz riscv-isa-sim-d6d919ee5b061add58b159b6551235241744c91f.tar.bz2 | |
Add Zicond to disassembler
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/disasm.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 8722cdb..7834799 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -2154,6 +2154,11 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DISASM_INSN("cbo.zero", cbo_zero, 0, {&base_only_address}); } + if (isa->extension_enabled(EXT_ZICOND)) { + DEFINE_RTYPE(czero_eqz); + DEFINE_RTYPE(czero_nez); + } + if (isa->extension_enabled(EXT_ZKND) || isa->extension_enabled(EXT_ZKNE)) { DISASM_INSN("aes64ks1i", aes64ks1i, 0, {&xrd, &xrs1, &rcon}); |