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author | Daniel Lustig <dlustig@nvidia.com> | 2021-07-20 13:30:16 -0400 |
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committer | GitHub <noreply@github.com> | 2021-07-20 10:30:16 -0700 |
commit | cb8f09a4d6fed30527fdd832b885c898b4591a5f (patch) | |
tree | d29859362cdb20f83e57899bacdfad628756c92d /disasm | |
parent | ec6f7b08ff59929313de1cff90973f34c5747ea9 (diff) | |
download | riscv-isa-sim-cb8f09a4d6fed30527fdd832b885c898b4591a5f.zip riscv-isa-sim-cb8f09a4d6fed30527fdd832b885c898b4591a5f.tar.gz riscv-isa-sim-cb8f09a4d6fed30527fdd832b885c898b4591a5f.tar.bz2 |
Priv virtual memory updates (#750)
* Priv virtual memory updates
* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set
* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)
* Add Svinval instructions
Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...
If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.
* Svinval: use #include rather than copying code
..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions
Thanks to @aswaterman for the suggestion
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 1c26c43..fe1e24e 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -662,6 +662,12 @@ disassembler_t::disassembler_t(int xlen) DEFINE_NOARG(fence_i); DEFINE_SFENCE_TYPE(sfence_vma); + DEFINE_NOARG(sfence_w_inval); + DEFINE_NOARG(sfence_inval_ir); + DEFINE_SFENCE_TYPE(sinval_vma); + DEFINE_SFENCE_TYPE(hinval_vvma); + DEFINE_SFENCE_TYPE(hinval_gvma); + add_insn(new disasm_insn_t("csrr", match_csrrs, mask_csrrs | mask_rs1, {&xrd, &csr})); add_insn(new disasm_insn_t("csrw", match_csrrw, mask_csrrw | mask_rd, {&csr, &xrs1})); add_insn(new disasm_insn_t("csrs", match_csrrs, mask_csrrs | mask_rd, {&csr, &xrs1})); |