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author | Andrew Waterman <andrew@sifive.com> | 2020-09-17 23:19:14 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2020-10-22 17:00:11 -0700 |
commit | cab796f546e4f2fa4e19d7804d008338267e8cda (patch) | |
tree | bc34c5d77a3bc5fb1bd5d16b9f644b46705b2aa8 /disasm | |
parent | 2622defd0cca6cc59a80227f5fa909926f44d42e (diff) | |
download | riscv-isa-sim-cab796f546e4f2fa4e19d7804d008338267e8cda.zip riscv-isa-sim-cab796f546e4f2fa4e19d7804d008338267e8cda.tar.gz riscv-isa-sim-cab796f546e4f2fa4e19d7804d008338267e8cda.tar.bz2 |
Start adding B ext to disassembler
Diffstat (limited to 'disasm')
-rw-r--r-- | disasm/disasm.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 150250e..30ce651 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -542,6 +542,19 @@ disassembler_t::disassembler_t(int xlen) DEFINE_RTYPE(remw); DEFINE_RTYPE(remuw); + DEFINE_RTYPE(sh1add); + DEFINE_RTYPE(sh2add); + DEFINE_RTYPE(sh3add); + DEFINE_RTYPE(sh1addu_w); + DEFINE_RTYPE(sh2addu_w); + DEFINE_RTYPE(sh3addu_w); + DEFINE_RTYPE(addwu); + DEFINE_RTYPE(subwu); + DEFINE_ITYPE(addiwu); + DEFINE_RTYPE(ror); + DEFINE_RTYPE(rol); + DEFINE_ITYPE_SHIFT(rori); + DEFINE_NOARG(ecall); DEFINE_NOARG(ebreak); DEFINE_NOARG(uret); |