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| author | Atul Khare <atulkhare@rivosinc.com> | 2023-06-14 16:49:40 -0700 |
|---|---|---|
| committer | Atul Khare <atulkhare@rivosinc.com> | 2023-07-26 09:10:31 -0700 |
| commit | c927773dd1584d870dd60a1cf86c0a8f0d138dd4 (patch) | |
| tree | b5398b210a0437b256f9cf69b80ef7280fe2c302 /disasm | |
| parent | 62178539f8377805705fd6d857338c04b52ef60f (diff) | |
| download | riscv-isa-sim-c927773dd1584d870dd60a1cf86c0a8f0d138dd4.zip riscv-isa-sim-c927773dd1584d870dd60a1cf86c0a8f0d138dd4.tar.gz riscv-isa-sim-c927773dd1584d870dd60a1cf86c0a8f0d138dd4.tar.bz2 | |
Add Smcntrpmf functionality
If Smcntrpmf is enabled, mcycle / minstret increment only if counting
for the privilege level isn't inhibited in mcyclecfg / minstretcfg.
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/isa_parser.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index f4d9da4..d5dc439 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -290,6 +290,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_SMCSRIND] = true; } else if (ext_str == "sscsrind") { extension_table[EXT_SSCSRIND] = true; + } else if (ext_str == "smcntrpmf") { + extension_table[EXT_SMCNTRPMF] = true; } else if (ext_str[0] == 'x') { extension_table['X'] = true; if (ext_str.size() == 1) { |