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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-20 14:20:46 -0700 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-21 10:29:19 -0700 |
| commit | 9925435513d001027dc6fea1584fefd5b9bfb249 (patch) | |
| tree | e8ec8b7e27ada9be0b24f6d0d4306b4170d734d3 /disasm | |
| parent | 24d5693930b1e5657971941a64cb3bd9165e76d4 (diff) | |
| download | riscv-isa-sim-9925435513d001027dc6fea1584fefd5b9bfb249.zip riscv-isa-sim-9925435513d001027dc6fea1584fefd5b9bfb249.tar.gz riscv-isa-sim-9925435513d001027dc6fea1584fefd5b9bfb249.tar.bz2 | |
Allow disassembly from implementations that are not full V
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 5c0e9e0..343fff7 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1455,7 +1455,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DISASM_INSN("cm.jalt", cm_jalt, 0, {&rvcm_jt_index}); } - if (isa->extension_enabled('V')) { + if (isa->has_any_vector()) { DISASM_INSN("vsetivli", vsetivli, 0, {&xrd, &zimm5, &v_vtype}); DISASM_INSN("vsetvli", vsetvli, 0, {&xrd, &xrs1, &v_vtype}); DEFINE_RTYPE(vsetvl); |