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| author | Andrew Waterman <andrew@sifive.com> | 2022-07-18 15:10:53 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-18 15:10:53 -0700 |
| commit | 84b9d03c088af3a92505c82ff3160d984387248c (patch) | |
| tree | c9df154cb7ec58a7d15a62776cbbf0bf522170eb /disasm | |
| parent | 3742db886a8ae7b03c5e7e0ececf997a2fc16cfd (diff) | |
| parent | c0b3fdcbaba99576393c57607985a0009bb2ebb1 (diff) | |
| download | riscv-isa-sim-84b9d03c088af3a92505c82ff3160d984387248c.zip riscv-isa-sim-84b9d03c088af3a92505c82ff3160d984387248c.tar.gz riscv-isa-sim-84b9d03c088af3a92505c82ff3160d984387248c.tar.bz2 | |
Merge pull request #1041 from plctlab/plct-new-csrs
add support for m/henvcfgh and mconfigptr CSRs
Diffstat (limited to 'disasm')
0 files changed, 0 insertions, 0 deletions