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| author | Atul Khare <atulkhare@rivosinc.com> | 2023-07-10 15:58:44 -0700 |
|---|---|---|
| committer | Atul Khare <atulkhare@rivosinc.com> | 2023-07-19 14:22:51 -0700 |
| commit | 2d802093471e1c0515e3f58a41da4451afa5103e (patch) | |
| tree | 8611e9e1f7d25c7174d88b2481f4b6d601104eac /disasm | |
| parent | 432c9ee97613ec73bbb10591f0cef9c1c93b4284 (diff) | |
| download | riscv-isa-sim-2d802093471e1c0515e3f58a41da4451afa5103e.zip riscv-isa-sim-2d802093471e1c0515e3f58a41da4451afa5103e.tar.gz riscv-isa-sim-2d802093471e1c0515e3f58a41da4451afa5103e.tar.bz2 | |
Add Smcsrind/Sscsrind extensions
Diffstat (limited to 'disasm')
| -rw-r--r-- | disasm/isa_parser.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index c18a72d..f4d9da4 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -286,6 +286,10 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) } else if (ext_str == "zvkt") { } else if (ext_str == "sstc") { extension_table[EXT_SSTC] = true; + } else if (ext_str == "smcsrind") { + extension_table[EXT_SMCSRIND] = true; + } else if (ext_str == "sscsrind") { + extension_table[EXT_SSCSRIND] = true; } else if (ext_str[0] == 'x') { extension_table['X'] = true; if (ext_str.size() == 1) { |