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| author | Ved Shanbhogue <ved@rivosinc.com> | 2024-05-04 15:30:10 -0500 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-05-06 18:21:06 -0500 |
| commit | c5229c3f5f4b6404977bb4134f1a0bda5207ff90 (patch) | |
| tree | fd9c817dd725bd138d80782915b59379b809780f /disasm/disasm.cc | |
| parent | 7438d1e69286470b7aaa0a713fd853fdf5c12416 (diff) | |
| download | riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.zip riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.tar.gz riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.tar.bz2 | |
Add Zawrs extension
Diffstat (limited to 'disasm/disasm.cc')
| -rw-r--r-- | disasm/disasm.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 6716e5b..7c07ec3 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -880,6 +880,11 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_XAMO(amocas_h) } + if (isa->extension_enabled(EXT_ZAWRS)) { + DEFINE_NOARG(wrs_sto); + DEFINE_NOARG(wrs_nto); + } + if (isa->extension_enabled(EXT_ZICFILP)) { // lpad encodes as `auipc x0, label`, so it needs to be added before auipc // for higher disassembling priority |