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authorTim Newsome <tim@sifive.com>2016-04-24 08:54:19 -0700
committerTim Newsome <tim@sifive.com>2016-05-23 12:12:11 -0700
commitd999dfc0d41a119730ff8944d37dbee88bf99723 (patch)
tree2268c9d7d5f122fb81253d10bd05901eaff0ff62 /debug_rom
parent191671a2015136c429394fd3051e4a9c1ff45352 (diff)
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Add debug_module bus device.
This should replace the ROM hack I implemented earlier, but for now both exist together. Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
Diffstat (limited to 'debug_rom')
-rw-r--r--debug_rom/Makefile2
-rwxr-xr-xdebug_rom/debug_rom.S19
-rw-r--r--debug_rom/debug_rom.h8
3 files changed, 14 insertions, 15 deletions
diff --git a/debug_rom/Makefile b/debug_rom/Makefile
index d66b84f..9d286c9 100644
--- a/debug_rom/Makefile
+++ b/debug_rom/Makefile
@@ -5,7 +5,7 @@ CC = $(RISCV)/bin/riscv64-unknown-elf-gcc
OBJCOPY = $(RISCV)/bin/riscv64-unknown-elf-objcopy
%.o: %.S
- $(CC) -c $<
+ $(CC) -I.. -c $<
debug_rom.h: debug_rom.raw
xxd -i $^ | sed "s/^unsigned/static const unsigned/" > $@
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 577edbb..7130364 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -1,6 +1,8 @@
# This code should be functional. Doesn't have to be optimal.
# I'm writing it to prove that it can be done.
+#include "riscv/encoding.h"
+
# TODO: Update these constants once they're finalized in the doc.
#define DCSR 0x790
@@ -10,16 +12,13 @@
#define DSCRATCH 0x792
-#define MCPUID 0xf00
-#define MHARTID 0xf10
-
# TODO: Should be 0x400
#define DEBUG_RAM (-0x400)
#define DEBUG_RAM_SIZE 64
-#define SETHALTNOT 0x100
-#define CLEARHALTNOT 0x104
-#define CLEARDEBINT 0x108
+# TODO: Should be 0x100, 0x108
+#define SETHALTNOT (-0x100)
+#define CLEARDEBINT (-0x108)
.global entry
.global resume
@@ -31,7 +30,7 @@ entry: j _entry
resume:
# Clear debug interrupt.
clear_debint:
- csrr s1, MHARTID
+ csrr s1, CSR_MHARTID
sw s1, CLEARDEBINT(zero)
clear_debint_loop:
csrr s1, DCSR
@@ -39,7 +38,7 @@ clear_debint_loop:
bnez s1, clear_debint_loop
# Restore s1.
- csrr s1, MCPUID
+ csrr s1, CSR_MISA
bltz s1, restore_not_32
restore_32:
lw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
@@ -78,7 +77,7 @@ _entry:
jdebugram:
# Save s1 so that the debug program can use two registers.
- csrr s0, MCPUID
+ csrr s0, CSR_MISA
bltz s0, save_not_32
save_32:
sw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
@@ -94,7 +93,7 @@ save_128:
jr zero, DEBUG_RAM
spontaneous_halt:
- csrr s0, MHARTID
+ csrr s0, CSR_MHARTID
sw s0, SETHALTNOT(zero)
csrsi DCSR, DCSR_HALT_OFFSET
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index 10c4fef..79162c2 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -1,17 +1,17 @@
static const unsigned char debug_rom_raw[] = {
- 0x6f, 0x00, 0x40, 0x05, 0xf3, 0x24, 0x00, 0xf1, 0x23, 0x24, 0x90, 0x10,
+ 0x6f, 0x00, 0x40, 0x05, 0xf3, 0x24, 0x50, 0xf1, 0x23, 0x2c, 0x90, 0xee,
0xf3, 0x24, 0x00, 0x79, 0x93, 0xf4, 0x04, 0x40, 0xe3, 0x9c, 0x04, 0xfe,
- 0xf3, 0x24, 0x00, 0xf0, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0xc3,
+ 0xf3, 0x24, 0x00, 0xf1, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0xc3,
0x6f, 0x00, 0x80, 0x01, 0x93, 0x94, 0x14, 0x00, 0x63, 0xc6, 0x04, 0x00,
0x83, 0x34, 0x80, 0xc3, 0x6f, 0x00, 0x80, 0x00, 0x13, 0x00, 0x00, 0x00,
0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x84, 0x00, 0x63, 0x04, 0x04, 0x00,
0x6f, 0x00, 0x40, 0x05, 0x73, 0x24, 0x20, 0x79, 0x73, 0x00, 0x00, 0x10,
0x73, 0x10, 0x24, 0x79, 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x74, 0x00,
- 0x13, 0x04, 0xd4, 0xff, 0x63, 0x16, 0x04, 0x02, 0x73, 0x24, 0x00, 0xf0,
+ 0x13, 0x04, 0xd4, 0xff, 0x63, 0x16, 0x04, 0x02, 0x73, 0x24, 0x00, 0xf1,
0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0xc2, 0x67, 0x00, 0x00, 0xc0,
0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00, 0x23, 0x3c, 0x90, 0xc2,
0x67, 0x00, 0x00, 0xc0, 0x13, 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0xc0,
- 0x73, 0x24, 0x00, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x73, 0xe0, 0x01, 0x79,
+ 0x73, 0x24, 0x50, 0xf1, 0x23, 0x20, 0x80, 0xf0, 0x73, 0xe0, 0x01, 0x79,
0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x04, 0x40, 0xe3, 0x0c, 0x04, 0xfe,
0x6f, 0xf0, 0x1f, 0xfc
};