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| author | Tim Newsome <tim@sifive.com> | 2016-04-27 13:52:54 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 54bd259cd529294e9c0967bd0e9e20d8fa30dc3b (patch) | |
| tree | a2d74fa73f1757cb1a986c0c4dbf9b863a0d20f8 /debug_rom | |
| parent | 7baa7795ba6b878f1dc859f4d4ee239bb569c750 (diff) | |
| download | riscv-isa-sim-54bd259cd529294e9c0967bd0e9e20d8fa30dc3b.zip riscv-isa-sim-54bd259cd529294e9c0967bd0e9e20d8fa30dc3b.tar.gz riscv-isa-sim-54bd259cd529294e9c0967bd0e9e20d8fa30dc3b.tar.bz2 | |
Refactor how we track in-progress operations.
I think the functionality is unchanged.
Diffstat (limited to 'debug_rom')
| -rwxr-xr-x | debug_rom/debug_rom.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index ca58ee4..9825d48 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -32,6 +32,7 @@ resume: clear_debint: csrr s1, CSR_MHARTID sw s1, CLEARDEBINT(zero) + # TODO: race: what if the debugger sets debug int at this point? clear_debint_loop: csrr s1, DCSR andi s1, s1, (1<<DCSR_DEBUGINT_OFFSET) |