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| author | Andrew Waterman <aswaterman@gmail.com> | 2018-03-21 17:19:16 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-03-21 17:19:16 -0700 |
| commit | 1da69b975beeda193d5fa47950be5883ca20ad13 (patch) | |
| tree | 520abe609d8e2401afc140910bb2b417b8a415c5 /debug_rom/debug_rom.S | |
| parent | ec79312862ebdd597cc0f63e002e14f31c36deb0 (diff) | |
| download | riscv-isa-sim-1da69b975beeda193d5fa47950be5883ca20ad13.zip riscv-isa-sim-1da69b975beeda193d5fa47950be5883ca20ad13.tar.gz riscv-isa-sim-1da69b975beeda193d5fa47950be5883ca20ad13.tar.bz2 | |
Implement Hauser misa.C misalignment proposal (#187)
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7
- Reads of xEPC[1] are masked when RVC is disabled
- Writes to MISA are suppressed if they would cause a misaligned fetch
- Misaligned PCs no longer need to be checked upon fetch
Diffstat (limited to 'debug_rom/debug_rom.S')
0 files changed, 0 insertions, 0 deletions