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| author | Tim Newsome <tim@sifive.com> | 2022-07-30 10:28:58 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-07-30 10:28:58 -0700 |
| commit | 9e042c7bb1ab3601b018182b52c9ee6c29d45b42 (patch) | |
| tree | 4d51dbc5065945c8ff50da9f97b5b7f2b2e82a04 /debug_rom/debug_rom.S | |
| parent | 4d985feb4e65fd09e6fd9f6f5e9c534c2e522892 (diff) | |
| download | riscv-isa-sim-debug_rom_fence.zip riscv-isa-sim-debug_rom_fence.tar.gz riscv-isa-sim-debug_rom_fence.tar.bz2 | |
Move fence inside entry_loop.debug_rom_fence
This greatly reduces the amount of spinning in the debug loop spike does
when DEBUG_ROM_FLAGS are written by the debug module, because now it's
not getting a cached version over and over again.
Test using riscv-tests/debug. Debugging still works.
Diffstat (limited to 'debug_rom/debug_rom.S')
| -rwxr-xr-x | debug_rom/debug_rom.S | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S index 2d36139..a1ddfe5 100755 --- a/debug_rom/debug_rom.S +++ b/debug_rom/debug_rom.S @@ -20,9 +20,6 @@ exception: jal zero, _exception _entry: - // This fence is required because the execution may have written something - // into the Abstract Data or Program Buffer registers. - fence csrw CSR_DSCRATCH0, s0 // Save s0 to allow signaling MHARTID // We continue to let the hart know that we are halted in order that @@ -30,6 +27,8 @@ _entry: // We keep checking both whether there is something the debugger wants // us to do, or whether we should resume. entry_loop: + // Make sure that we don't access a cached version of DEBUG_ROM_FLAGS + fence csrr s0, CSR_MHARTID sw s0, DEBUG_ROM_HALTED(zero) lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here. |