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| author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-20 14:30:19 -0700 |
|---|---|---|
| committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-21 10:29:20 -0700 |
| commit | 3b6a8fa06ec04bee5634a52b01a4df0d5a91f826 (patch) | |
| tree | 432d62cf15ce73e74b2bb16bdf2cdee5ed6d266f /configure | |
| parent | 0f4642ee44ba026bed7bc6f8b0d738de8cc9d948 (diff) | |
| download | riscv-isa-sim-3b6a8fa06ec04bee5634a52b01a4df0d5a91f826.zip riscv-isa-sim-3b6a8fa06ec04bee5634a52b01a4df0d5a91f826.tar.gz riscv-isa-sim-3b6a8fa06ec04bee5634a52b01a4df0d5a91f826.tar.bz2 | |
Remove all --varch parsing
Diffstat (limited to 'configure')
| -rwxr-xr-x | configure | 17 |
1 files changed, 0 insertions, 17 deletions
@@ -739,7 +739,6 @@ with_boost_asio with_boost_regex with_isa with_priv -with_varch with_target enable_dual_endian ' @@ -1407,8 +1406,6 @@ Optional Packages: --with-isa=RV64IMAFDC_zicntr_zihpm Sets the default RISC-V ISA --with-priv=MSU Sets the default RISC-V privilege modes supported - --with-varch=vlen:128,elen:64 - Sets the default vector config --with-target=riscv64-unknown-elf Sets the default target config @@ -6593,20 +6590,6 @@ fi -# Check whether --with-varch was given. -if test ${with_varch+y} -then : - withval=$with_varch; -printf "%s\n" "#define DEFAULT_VARCH \"$withval\"" >>confdefs.h - -else $as_nop - -printf "%s\n" "#define DEFAULT_VARCH \"vlen:128,elen:64\"" >>confdefs.h - -fi - - - # Check whether --with-target was given. if test ${with_target+y} then : |