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author | Andrew Waterman <andrew@sifive.com> | 2017-04-05 20:37:01 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-04-05 20:39:24 -0700 |
commit | 1132fdf4f07dfbfba237af7b0cfac3cae543a79b (patch) | |
tree | e94bcf8bba579f661b78fbdcf1bc267c36f08ef4 /configure | |
parent | f2e8eb28cca2a5f49cea9f37774058718f795fdd (diff) | |
download | riscv-isa-sim-1132fdf4f07dfbfba237af7b0cfac3cae543a79b.zip riscv-isa-sim-1132fdf4f07dfbfba237af7b0cfac3cae543a79b.tar.gz riscv-isa-sim-1132fdf4f07dfbfba237af7b0cfac3cae543a79b.tar.bz2 |
Add --enable-misaligned option for misaligned ld/st support
Resolves #93
Diffstat (limited to 'configure')
-rwxr-xr-x | configure | 16 |
1 files changed, 16 insertions, 0 deletions
@@ -706,6 +706,7 @@ with_fesvr enable_commitlog enable_histogram enable_dirty +enable_misaligned ' ac_precious_vars='build_alias host_alias @@ -1352,6 +1353,8 @@ Optional Features: --enable-histogram Enable PC histogram generation --enable-dirty Enable hardware management of PTE accessed and dirty bits + --enable-misaligned Enable hardware support for misaligned loads and + stores Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] @@ -4681,6 +4684,19 @@ $as_echo "#define RISCV_ENABLE_DIRTY /**/" >>confdefs.h fi +# Check whether --enable-misaligned was given. +if test "${enable_misaligned+set}" = set; then : + enableval=$enable_misaligned; +fi + +if test "x$enable_misaligned" = "xyes"; then : + + +$as_echo "#define RISCV_ENABLE_MISALIGNED /**/" >>confdefs.h + + +fi + |