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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 20:27:28 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-23 21:53:53 -0700 |
| commit | 5a208b28a23fa408d12f91f838564575a4270043 (patch) | |
| tree | edff7bf568740f04927a4b9c57fee3bd724d503d /configure.ac | |
| parent | f9fbe2205343b5c0cd49f6021eb144e79373959f (diff) | |
| download | riscv-isa-sim-5a208b28a23fa408d12f91f838564575a4270043.zip riscv-isa-sim-5a208b28a23fa408d12f91f838564575a4270043.tar.gz riscv-isa-sim-5a208b28a23fa408d12f91f838564575a4270043.tar.bz2 | |
rvv: restrict segment load register rule
For unit-strided and stride segment load, mask register can't
overlap destination register if masked
ref:
https://github.com/riscv/riscv-v-spec/pull/395
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'configure.ac')
0 files changed, 0 insertions, 0 deletions