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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-20 01:48:03 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-20 01:48:58 -0700 |
| commit | 59a9277ac1e3f9aca630fb035d1dbacaa091e375 (patch) | |
| tree | c31c933c69e5e3217d88333f4d4fe2c7143ad078 /configure.ac | |
| parent | f3055afa55125627be0b64bf7b8bd1c876d9bc79 (diff) | |
| download | riscv-isa-sim-59a9277ac1e3f9aca630fb035d1dbacaa091e375.zip riscv-isa-sim-59a9277ac1e3f9aca630fb035d1dbacaa091e375.tar.gz riscv-isa-sim-59a9277ac1e3f9aca630fb035d1dbacaa091e375.tar.bz2 | |
ebreak should write mtval with 0, not pc
Resolves #426
The relevant passage in the spec does not mention software breakpoints
as one of the cases that cause mtval to be set to a nonzero value:
https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202
Diffstat (limited to 'configure.ac')
0 files changed, 0 insertions, 0 deletions