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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-18 17:24:04 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-18 17:24:04 -0800 |
| commit | 67cd71d9ec5087bdcfa8fda1172abc0049df8455 (patch) | |
| tree | 2f9df81c647d287abba097c8f185931d82bfe42a /config.h.in | |
| parent | eace5599606034850e28eef63f1e00eaf8eb6d26 (diff) | |
| download | riscv-isa-sim-67cd71d9ec5087bdcfa8fda1172abc0049df8455.zip riscv-isa-sim-67cd71d9ec5087bdcfa8fda1172abc0049df8455.tar.gz riscv-isa-sim-67cd71d9ec5087bdcfa8fda1172abc0049df8455.tar.bz2 | |
Make HW setting of PTE A/D bits optional (by configure arg)
https://github.com/riscv/riscv-isa-manual/issues/14
Diffstat (limited to 'config.h.in')
| -rw-r--r-- | config.h.in | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/config.h.in b/config.h.in index a4070ff..566b1bc 100644 --- a/config.h.in +++ b/config.h.in @@ -66,6 +66,9 @@ /* Enable commit log generation */ #undef RISCV_ENABLE_COMMITLOG +/* Enable hardware management of PTE accessed and dirty bits */ +#undef RISCV_ENABLE_DIRTY + /* Enable PC histogram generation */ #undef RISCV_ENABLE_HISTOGRAM |