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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 16:05:39 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:44:42 -0800 |
| commit | 1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca (patch) | |
| tree | ba7769d7a07dfd64f7a998dc6e8ad3ebd5f65cf8 /config.h.in | |
| parent | b3dfcf1523122cf1fb907fdb75dcdc4d655b7b06 (diff) | |
| download | riscv-isa-sim-1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca.zip riscv-isa-sim-1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca.tar.gz riscv-isa-sim-1aac9da38f24c5f8eafe57bfb9a0f7820c1cbaca.tar.bz2 | |
Delete --enable-misaligned configure option
Diffstat (limited to 'config.h.in')
| -rw-r--r-- | config.h.in | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/config.h.in b/config.h.in index c89b10d..01d776c 100644 --- a/config.h.in +++ b/config.h.in @@ -105,9 +105,6 @@ /* Enable support for running target in either endianness */ #undef RISCV_ENABLE_DUAL_ENDIAN -/* Enable hardware support for misaligned loads and stores */ -#undef RISCV_ENABLE_MISALIGNED - /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SOFTFLOAT_ENABLED |