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| author | Andrew Waterman <andrew@sifive.com> | 2017-04-05 20:37:01 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-05 20:39:24 -0700 |
| commit | 1132fdf4f07dfbfba237af7b0cfac3cae543a79b (patch) | |
| tree | e94bcf8bba579f661b78fbdcf1bc267c36f08ef4 /config.h.in | |
| parent | f2e8eb28cca2a5f49cea9f37774058718f795fdd (diff) | |
| download | riscv-isa-sim-1132fdf4f07dfbfba237af7b0cfac3cae543a79b.zip riscv-isa-sim-1132fdf4f07dfbfba237af7b0cfac3cae543a79b.tar.gz riscv-isa-sim-1132fdf4f07dfbfba237af7b0cfac3cae543a79b.tar.bz2 | |
Add --enable-misaligned option for misaligned ld/st support
Resolves #93
Diffstat (limited to 'config.h.in')
| -rw-r--r-- | config.h.in | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/config.h.in b/config.h.in index 15b5850..137f195 100644 --- a/config.h.in +++ b/config.h.in @@ -75,6 +75,9 @@ /* Enable PC histogram generation */ #undef RISCV_ENABLE_HISTOGRAM +/* Enable hardware support for misaligned loads and stores */ +#undef RISCV_ENABLE_MISALIGNED + /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SOFTFLOAT_ENABLED |