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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 15:38:37 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:44:42 -0800 |
| commit | a11af65d0e30cd41fa25980686be701adcbb8ee0 (patch) | |
| tree | 019b1f9bab166f64e6bb04b4082839356906b0d6 /ci-tests | |
| parent | 8d084dbd092a916a2c26d9cb7f30d5651aa3181b (diff) | |
| download | riscv-isa-sim-a11af65d0e30cd41fa25980686be701adcbb8ee0.zip riscv-isa-sim-a11af65d0e30cd41fa25980686be701adcbb8ee0.tar.gz riscv-isa-sim-a11af65d0e30cd41fa25980686be701adcbb8ee0.tar.bz2 | |
Add --[no-]misaligned command-line options
They don't do anything yet.
Diffstat (limited to 'ci-tests')
| -rw-r--r-- | ci-tests/testlib.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/ci-tests/testlib.c b/ci-tests/testlib.c index 3d2d18d..e9b7daa 100644 --- a/ci-tests/testlib.c +++ b/ci-tests/testlib.c @@ -21,6 +21,7 @@ int main() "rv64gcv", "MSU", "vlen:128,elen:64", + false, endianness_little, 16, mem_cfg, |