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authorNeel Gala <neelgala@incoresemi.com>2022-02-24 21:14:23 +0530
committerNeel Gala <neelgala@incoresemi.com>2022-02-24 21:14:23 +0530
commit1b3a5b96f81fe5881e15f6b3ea00415bcb7e2aaf (patch)
tree6441f205dd615ffab1b56784b71186268484eec2 /arch_test_target
parent734855d986ba118717b2901b542cc1e09033bd07 (diff)
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adding ports to run F, D and E extension architectural tests on spike
Diffstat (limited to 'arch_test_target')
-rw-r--r--arch_test_target/spike/device/rv32e_unratified/C/Makefile.include40
-rw-r--r--arch_test_target/spike/device/rv32e_unratified/E/Makefile.include40
-rw-r--r--arch_test_target/spike/device/rv32e_unratified/M/Makefile.include40
-rw-r--r--arch_test_target/spike/device/rv32i_m/F/Makefile.include40
-rw-r--r--arch_test_target/spike/device/rv64i_m/D/Makefile.include41
-rw-r--r--arch_test_target/spike/model_test.h2
6 files changed, 202 insertions, 1 deletions
diff --git a/arch_test_target/spike/device/rv32e_unratified/C/Makefile.include b/arch_test_target/spike/device/rv32e_unratified/C/Makefile.include
new file mode 100644
index 0000000..7aad017
--- /dev/null
+++ b/arch_test_target/spike/device/rv32e_unratified/C/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+ $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX ?= riscv32-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+ -I$(ROOTDIR)/riscv-test-suite/env/ \
+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+ -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+ $$(<) -o $$@
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+ $$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+ $(COMPILE_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ; \
+ $(OBJ_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32ec \
+ +signature=$(*).signature.output +signature-granularity=4\
+ $<
+
+RUN_TARGET=\
+ $(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv32e_unratified/E/Makefile.include b/arch_test_target/spike/device/rv32e_unratified/E/Makefile.include
new file mode 100644
index 0000000..86b32e2
--- /dev/null
+++ b/arch_test_target/spike/device/rv32e_unratified/E/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+ $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX ?= riscv32-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+ -I$(ROOTDIR)/riscv-test-suite/env/ \
+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+ -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+ $$(<) -o $$@
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+ $$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+ $(COMPILE_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ; \
+ $(OBJ_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32e \
+ +signature=$(*).signature.output +signature-granularity=4\
+ $<
+
+RUN_TARGET=\
+ $(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv32e_unratified/M/Makefile.include b/arch_test_target/spike/device/rv32e_unratified/M/Makefile.include
new file mode 100644
index 0000000..141974d
--- /dev/null
+++ b/arch_test_target/spike/device/rv32e_unratified/M/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+ $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX ?= riscv32-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+ -I$(ROOTDIR)/riscv-test-suite/env/ \
+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+ -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+ $$(<) -o $$@
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+ $$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+ $(COMPILE_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ; \
+ $(OBJ_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32em \
+ +signature=$(*).signature.output +signature-granularity=4\
+ $<
+
+RUN_TARGET=\
+ $(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv32i_m/F/Makefile.include b/arch_test_target/spike/device/rv32i_m/F/Makefile.include
new file mode 100644
index 0000000..b5030c5
--- /dev/null
+++ b/arch_test_target/spike/device/rv32i_m/F/Makefile.include
@@ -0,0 +1,40 @@
+TARGET_SIM ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+ $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX ?= riscv32-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+ -I$(ROOTDIR)/riscv-test-suite/env/ \
+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+ -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+ $$(<) -o $$@
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+ $$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+ $(COMPILE_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ; \
+ $(OBJ_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv32if \
+ +signature=$(*).signature.output +signature-granularity=4\
+ $<
+
+RUN_TARGET=\
+ $(RUN_CMD)
diff --git a/arch_test_target/spike/device/rv64i_m/D/Makefile.include b/arch_test_target/spike/device/rv64i_m/D/Makefile.include
new file mode 100644
index 0000000..7c72d03
--- /dev/null
+++ b/arch_test_target/spike/device/rv64i_m/D/Makefile.include
@@ -0,0 +1,41 @@
+TARGET_SIM ?= spike
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+ $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RISCV_PREFIX ?= riscv64-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+ -I$(ROOTDIR)/riscv-test-suite/env/ \
+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+ -T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+ $$(<) -o $$@
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+ $$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+ $(COMPILE_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ; \
+ $(OBJ_CMD); \
+ if [ $$$$? -ne 0 ] ; \
+ then \
+ echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+ exit 1 ; \
+ fi ;
+
+RUN_CMD = $(TARGET_SIM) $(TARGET_FLAGS) --isa=rv64ifd \
+ +signature=$(*).signature.output +signature-granularity=4\
+ $<
+
+RUN_TARGET=\
+ $(RUN_CMD)
+
diff --git a/arch_test_target/spike/model_test.h b/arch_test_target/spike/model_test.h
index 6aeb1c2..e968e43 100644
--- a/arch_test_target/spike/model_test.h
+++ b/arch_test_target/spike/model_test.h
@@ -22,7 +22,7 @@
addi x1, x1, 4; \
li x1, 1; \
write_tohost: \
- sw x1, tohost, t5; \
+ sw x1, tohost, t1; \
self_loop: j self_loop;
#define RVMODEL_BOOT