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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-09 06:50:04 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-01-13 07:33:48 -0800 |
| commit | e75ba052d42b1af954c09adc815b541124c2ccce (patch) | |
| tree | ff5b2c8122bf125396f1f5eff684ac51c7bdb63a /README.md | |
| parent | fa2f63818aff194f96a0b81da103d6a4170173b2 (diff) | |
| download | riscv-isa-sim-e75ba052d42b1af954c09adc815b541124c2ccce.zip riscv-isa-sim-e75ba052d42b1af954c09adc815b541124c2ccce.tar.gz riscv-isa-sim-e75ba052d42b1af954c09adc815b541124c2ccce.tar.bz2 | |
doc: update vector extension version
0.8 is officially released.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -18,7 +18,7 @@ Spike supports the following RISC-V ISA features: - D extension, v2.2 - Q extension, v2.2 - C extension, v2.0 - - V extension, v0.8-draft-20191118, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_) + - V extension, v0.8, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_) - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) - Machine, Supervisor, and User modes, v1.11 - Debug v0.14 |