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author | YenHaoChen <howard25336284@gmail.com> | 2022-12-18 20:00:37 +0800 |
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committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-21 13:54:15 +0800 |
commit | 9f3372a8e3ee769e229328881a11a620a97495c4 (patch) | |
tree | d64c43ff8c5eca326bfe94568d895ef23a715470 /README.md | |
parent | 730152610adaf1828f7854eb5527b0a3f7aa5d79 (diff) | |
download | riscv-isa-sim-9f3372a8e3ee769e229328881a11a620a97495c4.zip riscv-isa-sim-9f3372a8e3ee769e229328881a11a620a97495c4.tar.gz riscv-isa-sim-9f3372a8e3ee769e229328881a11a620a97495c4.tar.bz2 |
triggers: add mcontrol6 trigger
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -38,7 +38,7 @@ Spike supports the following RISC-V ISA features: - Svpbmt extension, v1.0 - Svinval extension, v1.0 - Debug v0.14 - - 4 triggers support type=2 (mcontrol), type=4 (itrigger), type=5 (etrigger), and type=15 (disabled) + - 4 triggers support type=2 (mcontrol), type=4 (itrigger), type=5 (etrigger), type=6 (mcontrol6), and type=15 (disabled) - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 |