diff options
| author | Andrew Waterman <andrew@sifive.com> | 2022-05-12 16:20:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-12 16:20:57 -0700 |
| commit | 918cba10e103a4cb1405b7a481111b78c2274f28 (patch) | |
| tree | 89b2367c05127df186fd0af5ea46eb5a6e203de0 /README.md | |
| parent | 500d987d8750ff7e048c3e2fc0898863beb051cc (diff) | |
| download | riscv-isa-sim-918cba10e103a4cb1405b7a481111b78c2274f28.zip riscv-isa-sim-918cba10e103a4cb1405b7a481111b78c2274f28.tar.gz riscv-isa-sim-918cba10e103a4cb1405b7a481111b78c2274f28.tar.bz2 | |
Update README to reflect recently added extensions
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -27,6 +27,9 @@ Spike supports the following RISC-V ISA features: - Zbb extension, v1.0 - Zbc extension, v1.0 - Zbs extension, v1.0 + - Zfh and Zfhmin half-precision floating-point extensions, v1.0 + - Zmmul integer multiplication extension, v1.0 + - Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0 - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) - Machine, Supervisor, and User modes, v1.11 - Hypervisor extension, v1.0 |