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| author | liweiwei <liweiwei@iscas.ac.cn> | 2021-10-14 12:38:38 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-04 10:11:29 +0800 |
| commit | 8aaae32d1d8fc3d20d62aae3039d6591346e95de (patch) | |
| tree | beda9a270136c63562d80d4e7b5606c66db9f57b /README.md | |
| parent | 5de0c89c034cf64fdab8e36d2dc7488aa035d823 (diff) | |
| download | riscv-isa-sim-8aaae32d1d8fc3d20d62aae3039d6591346e95de.zip riscv-isa-sim-8aaae32d1d8fc3d20d62aae3039d6591346e95de.tar.gz riscv-isa-sim-8aaae32d1d8fc3d20d62aae3039d6591346e95de.tar.bz2 | |
Add support for freg command to read X regs when enable Zfinx
Update README
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -28,6 +28,7 @@ Spike supports the following RISC-V ISA features: - Zbc extension, v1.0 - Zbs extension, v1.0 - Zfh and Zfhmin half-precision floating-point extensions, v1.0 + - Zfinx extension, v1.0 - Zmmul integer multiplication extension, v1.0 - Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0 - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) |