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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2024-02-02 17:13:39 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-02-03 16:19:18 +0800 |
| commit | 6903ff698d2a6469b3773558d760b31a2947ae9f (patch) | |
| tree | 6da0bdf0f9aa4734b399f16dd11c14db4e751760 /README.md | |
| parent | 7c890632ec91104fe6ccd9f16f70842c4412a1fd (diff) | |
| download | riscv-isa-sim-6903ff698d2a6469b3773558d760b31a2947ae9f.zip riscv-isa-sim-6903ff698d2a6469b3773558d760b31a2947ae9f.tar.gz riscv-isa-sim-6903ff698d2a6469b3773558d760b31a2947ae9f.tar.bz2 | |
Update trigger description in README.md
The number of triggers is configurable since https://github.com/riscv-software-src/riscv-isa-sim/pull/1219.
The trigger description was for the limited implementation when developing the extension. All trigger types are supported now. The information isn't very useful anymore.
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -39,7 +39,6 @@ Spike supports the following RISC-V ISA features: - Svinval extension, v1.0 - Sdext extension, v1.0-STABLE - Sdtrig extension, v1.0-STABLE - - 4 triggers support type={2, 3, 4, 5, 6, 15} (mcontrol, icount, itrigger, etrigger, mcontrol6, disabled) - Smepmp extension v1.0 - Smstateen extension, v1.0 - Sscofpmf v0.5.2 |