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| author | Kito Cheng <kito.cheng@sifive.com> | 2020-11-03 09:27:31 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2020-11-03 09:27:31 +0800 |
| commit | 2a9849e3ab12a671dd9c2e480d00fc2a5eb83170 (patch) | |
| tree | 3be2e017ce4d39da08012e234f8e0a283f851fe4 /README.md | |
| parent | 1d30acb2d4e79744851c9899572945fd86a730ff (diff) | |
| download | riscv-isa-sim-2a9849e3ab12a671dd9c2e480d00fc2a5eb83170.zip riscv-isa-sim-2a9849e3ab12a671dd9c2e480d00fc2a5eb83170.tar.gz riscv-isa-sim-2a9849e3ab12a671dd9c2e480d00fc2a5eb83170.tar.bz2 | |
doc: update readme for bitmanip 0.92
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -18,6 +18,7 @@ Spike supports the following RISC-V ISA features: - D extension, v2.2 - Q extension, v2.2 - C extension, v2.0 + - B extension, v0.92 - V extension, v0.9, w/ Zvlsseg/Zvamo/Zvqmac, w/o Zvediv, (_requires a 64-bit host_) - Conformance to both RVWMO and RVTSO (Spike is sequentially consistent) - Machine, Supervisor, and User modes, v1.11 |