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author | Will Hawkins <8715530+hawkinsw@users.noreply.github.com> | 2020-11-29 19:09:50 -0500 |
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committer | GitHub <noreply@github.com> | 2020-11-29 16:09:50 -0800 |
commit | f4f6e12eeeabccc31853ab4e8570219d1f5cba37 (patch) | |
tree | 6861e5831a07a0725c659ce5133129f29ac619e1 | |
parent | 4b04d715298c7c0542badf30828f65d1f02e1c1d (diff) | |
download | riscv-isa-sim-f4f6e12eeeabccc31853ab4e8570219d1f5cba37.zip riscv-isa-sim-f4f6e12eeeabccc31853ab4e8570219d1f5cba37.tar.gz riscv-isa-sim-f4f6e12eeeabccc31853ab4e8570219d1f5cba37.tar.bz2 |
Fix #607: Add a core parameter to the interactive str command (#608)
Add a core parameter to the interactive str command. This makes it
possible for the spike user to specify the device whose memory contains
the NUL-terminated string to be printed.
-rw-r--r-- | riscv/interactive.cc | 17 | ||||
-rw-r--r-- | riscv/sim.cc | 6 |
2 files changed, 18 insertions, 5 deletions
diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 00e505d..009eb82 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -125,7 +125,7 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector<std::stri "vreg <core> [reg] # Display vector [reg] (all if omitted) in <core>\n" "pc <core> # Show current PC in <core>\n" "mem <hex addr> # Show contents of physical memory\n" - "str <hex addr> # Show NUL-terminated C string\n" + "str <core> <hex addr> # Show NUL-terminated C string at <hex addr> in core <core>\n" "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n" "until pc <core> <val> # Stop when PC in <core> hits <val>\n" "untiln pc <core> <val> # Run noisy and stop when PC in <core> hits <val>\n" @@ -363,13 +363,22 @@ void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::strin void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args) { - if(args.size() != 1) + if(args.size() != 1 && args.size() != 2) throw trap_interactive(); - reg_t addr = strtol(args[0].c_str(),NULL,16); + std::string addr_str = args[0]; + mmu_t* mmu = debug_mmu; + if(args.size() == 2) + { + processor_t *p = get_core(args[0]); + mmu = p->get_mmu(); + addr_str = args[1]; + } + + reg_t addr = strtol(addr_str.c_str(),NULL,16); char ch; - while((ch = debug_mmu->load_uint8(addr++))) + while((ch = mmu->load_uint8(addr++))) putchar(ch); putchar('\n'); diff --git a/riscv/sim.cc b/riscv/sim.cc index 20895d6..0261f86 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -351,9 +351,13 @@ char* sim_t::addr_to_mem(reg_t addr) { if (!paddr_ok(addr)) return NULL; auto desc = bus.find_device(addr); - if (auto mem = dynamic_cast<mem_t*>(desc.second)) + if (auto mem = dynamic_cast<mem_t*>(desc.second)) { if (addr - desc.first < mem->size()) return mem->contents() + (addr - desc.first); + } else if (auto mem = dynamic_cast<clint_t*>(desc.second)) { + fprintf(stdout, "clint_t\n"); + return NULL; + } return NULL; } |