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author | Andrew Waterman <andrew@sifive.com> | 2023-02-04 18:02:19 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-03-01 13:34:07 -0800 |
commit | ef1638be6cdb6cfb77d77f5ae233e5e196e40125 (patch) | |
tree | 07839eb485f33bd71701a0222fc4609eae01fabc | |
parent | b6d8da39bca349352b69913ef1b2b88b31ddc5b5 (diff) | |
download | riscv-isa-sim-ef1638be6cdb6cfb77d77f5ae233e5e196e40125.zip riscv-isa-sim-ef1638be6cdb6cfb77d77f5ae233e5e196e40125.tar.gz riscv-isa-sim-ef1638be6cdb6cfb77d77f5ae233e5e196e40125.tar.bz2 |
Correctly instantiate PLIC contexts for mixed-hart targets
This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.
Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor. In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.
-rw-r--r-- | riscv/devices.h | 3 | ||||
-rw-r--r-- | riscv/plic.cc | 13 | ||||
-rw-r--r-- | riscv/sim.cc | 2 |
3 files changed, 11 insertions, 7 deletions
diff --git a/riscv/devices.h b/riscv/devices.h index 4316c4f..0fa8885 100644 --- a/riscv/devices.h +++ b/riscv/devices.h @@ -12,6 +12,7 @@ #include <utility> class processor_t; +class sim_t; class bus_t : public abstract_device_t { public: @@ -96,7 +97,7 @@ struct plic_context_t { class plic_t : public abstract_device_t, public abstract_interrupt_controller_t { public: - plic_t(std::vector<processor_t*>&, bool smode, uint32_t ndev); + plic_t(sim_t*, uint32_t ndev); bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); void set_interrupt_level(uint32_t id, int lvl); diff --git a/riscv/plic.cc b/riscv/plic.cc index 45fadd7..5aa0923 100644 --- a/riscv/plic.cc +++ b/riscv/plic.cc @@ -1,6 +1,7 @@ #include <sys/time.h> #include "devices.h" #include "processor.h" +#include "sim.h" #define PLIC_MAX_CONTEXTS 15872 @@ -66,15 +67,17 @@ #define REG_SIZE 0x1000000 -plic_t::plic_t(std::vector<processor_t*>& procs, bool smode, uint32_t ndev) +plic_t::plic_t(sim_t* sim, uint32_t ndev) : num_ids(ndev + 1), num_ids_word(((ndev + 1) + (32 - 1)) / 32), max_prio((1UL << PLIC_PRIO_BITS) - 1), priority{}, level{} { - size_t contexts_per_hart = smode ? 2 : 1; - size_t num_contexts = procs.size() * (smode ? 2 : 1); + // PLIC contexts are contiguous in memory even if harts are discontiguous. + for (const auto& [hart_id, hart] : sim->get_harts()) { + contexts.push_back(plic_context_t(hart, true)); - for (size_t i = 0; i < num_contexts; i++) { - contexts.push_back(plic_context_t(procs[i / contexts_per_hart], i % contexts_per_hart == 0)); + if (hart->extension_enabled_const('S')) { + contexts.push_back(plic_context_t(hart, false)); + } } } diff --git a/riscv/sim.cc b/riscv/sim.cc index c623de1..a7ffc87 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -130,7 +130,7 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, reg_t plic_base; uint32_t plic_ndev; if (fdt_parse_plic(fdt, &plic_base, &plic_ndev, "riscv,plic0") == 0) { - plic.reset(new plic_t(procs, true, plic_ndev)); + plic.reset(new plic_t(this, plic_ndev)); bus.add_device(plic_base, plic.get()); intctrl = plic.get(); } |