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| author | Andrew Waterman <andrew@sifive.com> | 2023-02-28 15:13:09 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-28 15:13:09 -0800 |
| commit | d1ae27b7f843b35bd32778c54b4973d7aeffad52 (patch) | |
| tree | e1b7b44341f898ac6cd9e2bb59c40c290e8b6977 | |
| parent | 2badcfb88ffef42be9efa5eaa8a70effac26260b (diff) | |
| parent | 8f2994aa7ff27ba44a707d0ef7be12b9ee01d0a6 (diff) | |
| download | riscv-isa-sim-d1ae27b7f843b35bd32778c54b4973d7aeffad52.zip riscv-isa-sim-d1ae27b7f843b35bd32778c54b4973d7aeffad52.tar.gz riscv-isa-sim-d1ae27b7f843b35bd32778c54b4973d7aeffad52.tar.bz2 | |
Merge pull request #1259 from WadeGao/perf/wadegao_plic_num_id_words_init_logic_optimization
plic initialization optimize
| -rw-r--r-- | riscv/plic.cc | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/riscv/plic.cc b/riscv/plic.cc index aa91939..d0f1268 100644 --- a/riscv/plic.cc +++ b/riscv/plic.cc @@ -67,15 +67,12 @@ #define REG_SIZE 0x1000000 plic_t::plic_t(std::vector<processor_t*>& procs, bool smode, uint32_t ndev) - : procs(procs), contexts(procs.size() * (smode ? 2 : 1)) + : procs(procs), contexts(procs.size() * (smode ? 2 : 1)), + num_ids(ndev + 1), num_ids_word(((ndev + 1) + (32 - 1)) / 32), + max_prio((1UL << PLIC_PRIO_BITS) - 1) { size_t contexts_per_hart = smode ? 2 : 1; - num_ids = ndev + 1; - num_ids_word = num_ids / 32; - if ((num_ids_word * 32) < num_ids) - num_ids_word++; - max_prio = (1UL << PLIC_PRIO_BITS) - 1; memset(priority, 0, sizeof(priority)); memset(level, 0, sizeof(level)); |