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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-21 23:30:28 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2010-07-21 23:30:28 -0700 |
| commit | ceb91dab9cada03e1bc24e17a47ac162da73cdf4 (patch) | |
| tree | 424381979acab38b741414a8f39805632edd0a28 | |
| parent | d2c5b5c15930668588f88bd1186031dded771261 (diff) | |
| download | riscv-isa-sim-ceb91dab9cada03e1bc24e17a47ac162da73cdf4.zip riscv-isa-sim-ceb91dab9cada03e1bc24e17a47ac162da73cdf4.tar.gz riscv-isa-sim-ceb91dab9cada03e1bc24e17a47ac162da73cdf4.tar.bz2 | |
[pk,sim] removed cop0 console i/o support
| -rw-r--r-- | riscv/insns/mtc0.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/riscv/insns/mtc0.h b/riscv/insns/mtc0.h index f018cf6..d45d459 100644 --- a/riscv/insns/mtc0.h +++ b/riscv/insns/mtc0.h @@ -11,15 +11,6 @@ switch(insn.rtype.rs) case 3: ebase = sext32(RT & ~0xFFF); break; - case 8: - { - char ch = RT; - demand(1 == write(1,&ch,1),"wtf"); - break; - } - case 9: - printf("%ld insns retired\n",counters[0]); - exit(0); case 16: sim->set_tohost(sext32(RT)); |