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author | Andrew Waterman <andrew@sifive.com> | 2022-06-03 15:42:14 -0700 |
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committer | GitHub <noreply@github.com> | 2022-06-03 15:42:14 -0700 |
commit | caf5a420ef7414031368739e16d60f3f418aa6ac (patch) | |
tree | 886efe02151008fe6e178eba93d208c757521069 | |
parent | 901fedb22cbf5de22fab60a6c5d7236e350ecf64 (diff) | |
download | riscv-isa-sim-caf5a420ef7414031368739e16d60f3f418aa6ac.zip riscv-isa-sim-caf5a420ef7414031368739e16d60f3f418aa6ac.tar.gz riscv-isa-sim-caf5a420ef7414031368739e16d60f3f418aa6ac.tar.bz2 |
Remove nonstandard length encoding (#1023)
This was an artifact of an old P-extension draft that erroneously
allocated a reserved major opcode. The newer draft uses a different
opcode, so this hack is no longer needed.
-rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 9f13a42..6c90e21 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -69,7 +69,6 @@ const int NCSR = 4096; (((x) & 0x03) < 0x03 ? 2 : \ ((x) & 0x1f) < 0x1f ? 4 : \ ((x) & 0x3f) < 0x3f ? 6 : \ - ((x) & 0x7f) == 0x7f ? 4 : \ 8) #define MAX_INSN_LENGTH 8 #define PC_ALIGN 2 |