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author | Tim Newsome <tim@sifive.com> | 2018-03-19 09:35:55 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2018-03-19 09:35:55 -0700 |
commit | b4997aa4be6ab17b7a838b53e1ddea32726dad66 (patch) | |
tree | aa46de0e7ef641e1518253394073505d41ec0bac | |
parent | 403438d6096f4a6bf0ff924f60940acf51c529a5 (diff) | |
parent | 90bafe660b323250338fd564bb9ab4316576d59b (diff) | |
download | riscv-isa-sim-b4997aa4be6ab17b7a838b53e1ddea32726dad66.zip riscv-isa-sim-b4997aa4be6ab17b7a838b53e1ddea32726dad66.tar.gz riscv-isa-sim-b4997aa4be6ab17b7a838b53e1ddea32726dad66.tar.bz2 |
Merge pull request #182 from riscv/reset_bits
Implement debug havereset bits
-rw-r--r-- | riscv/debug_module.cc | 14 | ||||
-rw-r--r-- | riscv/debug_module.h | 8 | ||||
-rw-r--r-- | riscv/processor.cc | 2 | ||||
-rw-r--r-- | riscv/sim.cc | 5 | ||||
-rw-r--r-- | riscv/sim.h | 5 |
5 files changed, 33 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 74c3023..6f9359b 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -35,6 +35,7 @@ debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bu memset(halted, 0, sizeof(halted)); memset(debug_rom_flags, 0, sizeof(debug_rom_flags)); memset(resumeack, 0, sizeof(resumeack)); + memset(havereset, 0, sizeof(havereset)); memset(program_buffer, 0, program_buffer_bytes); program_buffer[4*progbufsize] = ebreak(); program_buffer[4*progbufsize+1] = ebreak() >> 8; @@ -387,6 +388,10 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) result = set_field(result, DMI_DMSTATUS_IMPEBREAK, dmstatus.impebreak); + result = set_field(result, DMI_DMSTATUS_ALLHAVERESET, + havereset[dmcontrol.hartsel]); + result = set_field(result, DMI_DMSTATUS_ANYHAVERESET, + havereset[dmcontrol.hartsel]); result = set_field(result, DMI_DMSTATUS_ALLNONEXISTENT, dmstatus.allnonexistant); result = set_field(result, DMI_DMSTATUS_ALLUNAVAIL, dmstatus.allunavail); result = set_field(result, DMI_DMSTATUS_ALLRUNNING, dmstatus.allrunning); @@ -664,6 +669,9 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); dmcontrol.hartsel = get_field(value, ((1L<<hartsellen)-1) << DMI_DMCONTROL_HARTSEL_OFFSET); + if (get_field(value, DMI_DMCONTROL_ACKHAVERESET)) { + havereset[dmcontrol.hartsel] = false; + } } processor_t *proc = current_proc(); if (proc) { @@ -755,3 +763,9 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) } return false; } + +void debug_module_t::proc_reset(unsigned id) +{ + havereset[id] = true; + halted[id] = false; +} diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 813c647..50107fc 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -19,6 +19,8 @@ typedef struct { typedef struct { bool impebreak; + bool allhavereset; + bool anyhavereset; bool allnonexistant; bool anynonexistant; bool allunavail; @@ -95,6 +97,9 @@ class debug_module_t : public abstract_device_t bool dmi_read(unsigned address, uint32_t *value); bool dmi_write(unsigned address, uint32_t value); + // Called when one of the attached harts was reset. + void proc_reset(unsigned id); + private: static const unsigned datasize = 2; // Size of program_buffer in 32-bit words, as exposed to the rest of the @@ -119,9 +124,10 @@ class debug_module_t : public abstract_device_t uint8_t debug_abstract[debug_abstract_size * 4]; uint8_t *program_buffer; uint8_t dmdata[datasize * 4]; - + bool halted[1024]; bool resumeack[1024]; + bool havereset[1024]; uint8_t debug_rom_flags[1024]; void write32(uint8_t *rom, unsigned int index, uint32_t value); diff --git a/riscv/processor.cc b/riscv/processor.cc index 35adc10..5a57c28 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -154,6 +154,8 @@ void processor_t::reset() if (ext) ext->reset(); // reset the extension + + sim->proc_reset(id); } // Count number of contiguous 0 bits starting from the LSB. diff --git a/riscv/sim.cc b/riscv/sim.cc index 81c5f6f..04fbe3c 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -364,3 +364,8 @@ void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) memcpy(&data, src, sizeof data); debug_mmu->store_uint64(taddr, data); } + +void sim_t::proc_reset(unsigned id) +{ + debug_module.proc_reset(id); +} diff --git a/riscv/sim.h b/riscv/sim.h index 9a0a10b..257de5b 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -24,6 +24,8 @@ public: // used for MMIO addresses virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0; + // Callback for processors to let the simulation know they were reset. + virtual void proc_reset(unsigned id) = 0; }; // this class encapsulates the processors and memory in a RISC-V machine. @@ -49,6 +51,9 @@ public: processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } + // Callback for processors to let the simulation know they were reset. + void proc_reset(unsigned id); + private: std::vector<std::pair<reg_t, mem_t*>> mems; mmu_t* debug_mmu; // debug port into main memory |