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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-20 17:17:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-20 17:17:17 -0800 |
| commit | b47e8c0a190ac17d2622d5554b21bc871d56847a (patch) | |
| tree | d0f53cba6d732e8ed7131455f4ef4373297cb9e5 | |
| parent | f478eef85192ef4ff41d47bce8ec887fecc414f8 (diff) | |
| download | riscv-isa-sim-b47e8c0a190ac17d2622d5554b21bc871d56847a.zip riscv-isa-sim-b47e8c0a190ac17d2622d5554b21bc871d56847a.tar.gz riscv-isa-sim-b47e8c0a190ac17d2622d5554b21bc871d56847a.tar.bz2 | |
Take M-mode interrupts over S-mode interrupts
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 706c0bc..29307fd 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -172,7 +172,8 @@ void processor_t::take_interrupt(reg_t pending_interrupts) reg_t sie = get_field(state.mstatus, MSTATUS_SIE); reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); - enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled; + if (enabled_interrupts == 0) + enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled; if (enabled_interrupts) throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts)); |