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author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-04-24 16:01:33 -0700 |
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committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2014-04-24 16:01:33 -0700 |
commit | acc42d79e283a31de4037fcf75d9e8af61073b51 (patch) | |
tree | 0e5d10c5fba17ceff42eed8367556ef1e50c0b2c | |
parent | e23899eae22505d001f94e9e0d00f7abc3191475 (diff) | |
download | riscv-isa-sim-acc42d79e283a31de4037fcf75d9e8af61073b51.zip riscv-isa-sim-acc42d79e283a31de4037fcf75d9e8af61073b51.tar.gz riscv-isa-sim-acc42d79e283a31de4037fcf75d9e8af61073b51.tar.bz2 |
fix disassembly of bnez and friends
-rw-r--r-- | spike/disasm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spike/disasm.cc b/spike/disasm.cc index b35c49e..f63dee1 100644 --- a/spike/disasm.cc +++ b/spike/disasm.cc @@ -145,7 +145,7 @@ disassembler_t::disassembler_t() const uint32_t match_rd_ra = 1UL << 7; const uint32_t mask_rs1 = 0x1fUL << 15; const uint32_t match_rs1_ra = 1UL << 15; - const uint32_t mask_rs2 = 0x1fUL << 15; + const uint32_t mask_rs2 = 0x1fUL << 20; const uint32_t mask_imm = 0xfffUL << 20; #define DECLARE_INSN(code, match, mask) \ |