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| author | Tim Newsome <tim@sifive.com> | 2020-03-30 11:34:32 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-30 11:34:32 -0700 |
| commit | 858ffef27f7a6ed117c58326ea81b0d1654ad3a2 (patch) | |
| tree | 0d98e77fa6a21f97e421e0d09da0c866675e5b9d | |
| parent | 5c315d3c3f760bd3c05654d5e75c4f3f7be70251 (diff) | |
| download | riscv-isa-sim-858ffef27f7a6ed117c58326ea81b0d1654ad3a2.zip riscv-isa-sim-858ffef27f7a6ed117c58326ea81b0d1654ad3a2.tar.gz riscv-isa-sim-858ffef27f7a6ed117c58326ea81b0d1654ad3a2.tar.bz2 | |
Assert that debug_module is initialized correctly. (#437)
This would have prevented the regression in #409.
| -rw-r--r-- | riscv/debug_module.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index ef26b28..5c7d2f1 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -77,6 +77,7 @@ debug_module_t::~debug_module_t() void debug_module_t::reset() { + assert(sim->nprocs() > 0); for (unsigned i = 0; i < sim->nprocs(); i++) { processor_t *proc = sim->get_core(i); if (proc) |