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| author | YenHaoChen <howard25336284@gmail.com> | 2024-08-29 16:05:42 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-08-29 16:10:12 +0800 |
| commit | 84a212e93bac83db1537c7ff14985c3c414f7f31 (patch) | |
| tree | 2e6910520a2a19fde8b20fe1a5298e126be552b1 | |
| parent | 272c149f37100780dc97df4661561f17ea5dc1d5 (diff) | |
| download | riscv-isa-sim-84a212e93bac83db1537c7ff14985c3c414f7f31.zip riscv-isa-sim-84a212e93bac83db1537c7ff14985c3c414f7f31.tar.gz riscv-isa-sim-84a212e93bac83db1537c7ff14985c3c414f7f31.tar.bz2 | |
pointer masking: Always apply sstatus.MXR regardless of effective V
ISA spec says "Setting MXR at HS-level overrides both VS-stage and G-stage execute-only permissions."
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index ea86900..38ecb65 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -614,7 +614,7 @@ void mmu_t::register_memtracer(memtracer_t* t) } reg_t mmu_t::get_pmlen(bool effective_virt, reg_t effective_priv, xlate_flags_t flags) const { - if (!proc || proc->get_xlen() != 64 || (proc->state.sstatus->readvirt(effective_virt) & MSTATUS_MXR) || flags.hlvx) + if (!proc || proc->get_xlen() != 64 || ((proc->state.sstatus->readvirt(false) | proc->state.sstatus->readvirt(effective_virt)) & MSTATUS_MXR) || flags.hlvx) return 0; reg_t pmm = 0; |