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author | Andrew Waterman <andrew@sifive.com> | 2019-10-07 14:35:03 +0200 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-10-07 14:35:03 +0200 |
commit | 7cdcdfb01cb2f70aeead3743d767f2fad5c64cbf (patch) | |
tree | dfdd374e11e3f00317ffb405d389732c449104d3 | |
parent | 9443c1dbac0301faf3a47c5e6914cc7dcb34983e (diff) | |
download | riscv-isa-sim-7cdcdfb01cb2f70aeead3743d767f2fad5c64cbf.zip riscv-isa-sim-7cdcdfb01cb2f70aeead3743d767f2fad5c64cbf.tar.gz riscv-isa-sim-7cdcdfb01cb2f70aeead3743d767f2fad5c64cbf.tar.bz2 |
update changelog
-rw-r--r-- | ChangeLog.md | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/ChangeLog.md b/ChangeLog.md index 2dedbd3..9d456c2 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -2,6 +2,9 @@ Version 1.0.1-dev ----------------- - Preliminary support for a subset of the Vector Extension, v0.7.1. - Support S-mode vectored interrupts (i.e. `stvec[0]` is now writable). +- Added support for dynamic linking of libraries containing MMIO devices. +- When the commit log is enabled at configure time (`--enable-commitlog`), + it must also be enabled at runtime with the `--log-commits` option. - Several debug-related additions and changes: - Added `hasel` debug feature. - Added `--dm-no-abstract-csr` command-line option. |