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| author | YenHaoChen <howard25336284@gmail.com> | 2022-12-18 19:37:59 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2022-12-21 13:29:19 +0800 |
| commit | 72daa815a21bf8557cebc6f3f98c17381c43833b (patch) | |
| tree | b0fffa0ee2003aa277945fe027ef8d30d7a93b47 | |
| parent | 015fc185a49b0853efeee1d2be8c0e1cebdc9fe5 (diff) | |
| download | riscv-isa-sim-72daa815a21bf8557cebc6f3f98c17381c43833b.zip riscv-isa-sim-72daa815a21bf8557cebc6f3f98c17381c43833b.tar.gz riscv-isa-sim-72daa815a21bf8557cebc6f3f98c17381c43833b.tar.bz2 | |
triggers: refactor: update trigger_t::mode_match()
| -rw-r--r-- | riscv/triggers.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 63de28d..e71670e 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -56,12 +56,12 @@ void trigger_t::tdata3_write(processor_t * const proc, const reg_t val) noexcept bool trigger_t::mode_match(state_t * const state) const noexcept { - if ((state->prv == PRV_M && !m) || - (state->prv == PRV_S && !(state->v ? vs : s)) || - (state->prv == PRV_U && !(state->v ? vu : u))) { - return false; + switch (state->prv) { + case PRV_M: return m; + case PRV_S: return state->v ? vs : s; + case PRV_U: return state->v ? vu : u; + default: assert(false); } - return true; } bool trigger_t::textra_match(processor_t * const proc) const noexcept |