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| author | YenHaoChen <howard25336284@gmail.com> | 2024-09-03 08:49:53 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-09-03 08:57:13 +0800 |
| commit | 6a1a5db16b60abaecd235f78f5d70716bf47c9a9 (patch) | |
| tree | 5f7cf18349f0c9c031e27649028fcf7d3a4dc404 | |
| parent | b47d0baab34a03268f936c1c9400d61c46d54d67 (diff) | |
| download | riscv-isa-sim-6a1a5db16b60abaecd235f78f5d70716bf47c9a9.zip riscv-isa-sim-6a1a5db16b60abaecd235f78f5d70716bf47c9a9.tar.gz riscv-isa-sim-6a1a5db16b60abaecd235f78f5d70716bf47c9a9.tar.bz2 | |
vector: disassemble: Let operand ordering be vd, [vf]s1, vs2 to vector widening floating-point fused multiply-add instructions
| -rw-r--r-- | disasm/disasm.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index bad2ec4..f1967d0 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1970,10 +1970,10 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DISASM_OPIV_WF_INSN(vfwadd); DISASM_OPIV_WF_INSN(vfwsub); DISASM_OPIV_VF_INSN(vfwmul); - DISASM_OPIV_VF_INSN(vfwmacc); - DISASM_OPIV_VF_INSN(vfwnmacc); - DISASM_OPIV_VF_INSN(vfwmsac); - DISASM_OPIV_VF_INSN(vfwnmsac); + DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwmacc); + DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwnmacc); + DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwmsac); + DISASM_OPIV_MULTIPLYADD_VF_INSN(vfwnmsac); #undef DISASM_OPIV_VF_INSN #undef DISASM_OPIV__F_INSN |